학술논문
Improving the Reliability of FPGA CRO PUFs
Document Type
Conference
Source
2023 33rd International Conference on Field-Programmable Logic and Applications (FPL) FPL Field-Programmable Logic and Applications (FPL), 2023 33rd International Conference on. :311-316 Sep, 2023
Subject
Language
ISSN
1946-1488
Abstract
This paper presents a novel technique that greatly improves the reliability of FPGA-based CRO PUFs. We improve upon existing CRO implementations and increase the number of configurations per CLB tile from 16 384 to 1.1 × 10 12 • To maximize reliability, each CRO pair must be configured to maximize its frequency difference. This requires using a novel technique that reduces the configuration search space from 1.1 × 10 12 to 256. Our CRO PUF achieves 100% reliability within the FPGA's maximum rated voltages. We believe that this is the first FPGA PUF that can achieve this level of reliability without the use of post-processing. We also show that in some cases, our CRO may be reliable enough to omit the ECC that is usually required in PUF-based key generation circuits. This allows our CRO PUF to provide the reliability required for key generation while reducing the latency, complexity, and area overhead of ECC algorithms.