학술논문
A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual/tripe gate oxide process
Document Type
Conference
Author
Shien-Yang Wu; Liaw, J.J.; Lin, C.Y.; Chiang, M.C.; Yang, C.K.; Cheng, J.Y.; Tsai, M.H.; Liu, M.Y.; Wu, P.H.; Chang, C.H.; Hu, L.C.; Lin, C.I.; Chen, H.F.; Chang, S.Y.; Wang, S.H.; Tong, P.Y.; Hsieh, Y.L.; Pan, K.H.; Hsieh, C.H.; Chen, C.H.; Yao, C.H.; Chen, C.C.; Lee, T.L.; Chang, C.W.; Lin, H.J.; Chen, S.C.; Shieh, J.H.; Jang, S.M.; Chen, K.S.; Ku, Y.; See, Y.C; Lo, W.J.
Source
2009 Symposium on VLSI Technology VLSI Technology, 2009 Symposium on. :210-211 Jun, 2009
Subject
Language
ISSN
0743-1562
2158-9682
2158-9682
Abstract
For the first time, we present good yielding 64Mb SRAM test-chip with the smallest cell using dual/triple gate oxide process flow in 28nm node. The low power technology platform continues scaling trend and extends SiON/poly technology beyond 32nm node with gate density of 2.3× higher than that of 45nm, and integrates high density (0.127um 2 ) and low Vccmin (0.155um 2 ) 6-T SRAM cells, low power transistors, analog/RF components and Cu-low-k interconnect [1]. Simultaneously available low standby (LSTP) and low operating power (LOP) transistors provide 25–40% speed improvement or 30–50% active power reduction over prior 45nm technology. Competitive mismatch (AVt of 2.86 mV.um) and 1/f noise characteristics, and enhanced MOM unit capacitance of 4.4 fF/um 2 (4 metal layers) with Q factor ≫100 at 2.4GHz are also achieved.