학술논문
A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM
Document Type
Conference
Author
Wu, Shien-Yang; Chou, C.W.; Lin, C.Y.; Chiang, M.C.; Yang, C.K.; Liu, M.Y.; Hu, L.C.; Chang, C.H.; Wu, P.H.; Lin, C.I.; Chen, H.F.; Chang, S.Y.; Wang, S.H.; Tong, P.Y.; Hsieh, Y.L.; Liaw, J.J.; Pan, K.H.; Hsieh, C.H.; Chen, C.H.; Cheng, J.Y.; Yao, C.H.; Wan, W.K.; Lee, T.L.; Huang, K.T.; Chen, C.C; Lin, K.C.; Yeh, L.Y.; Ku, K.C.; Chen, S.C.; Chang, C.W.; Lin, H.J.; Jang, S.M.; Lu, Y.C.; Shieh, J.H.; Tsai, M.H.; Song, J.Y.; Chen, K.S.; Chang, V.; Cheng, S.M.; Yang, S.H.; Diaz, C.H.; See, Y.C.; Liang, M.S.
Source
2007 IEEE International Electron Devices Meeting Electron Devices Meeting, 2007. IEDM 2007. IEEE International. :263-266 Dec, 2007
Subject
Language
ISSN
0163-1918
2156-017X
2156-017X
Abstract
For the first time, we present a state-of-the-art 32nm low power foundry technology integrated with 0.15um 2 6-T high density SRAM, low standby transistors, analog/RF functions and Cu/low-k interconnect for mobile SoC applications. To our knowledge, this is the smallest fully functional 2Mb SRAM test-chip for 32nm node. Low power transistors with Lg of 30nm achieve current drive of 700/380 uA/um at 1.1V and off-leakage current of 1 nA/um for NMOS and PMOS, respectively. An NPoly/NWell MOS varactor shows capacitance ratio of ≫5.0. The MOM unit capacitance of 3.5 fF/um 2 is achieved with only 4 metal layers.