학술논문
Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain
Document Type
Conference
Author
Barraud, S.; Lapras, V.; Samson, M.P.; Gaben, L.; Grenouillet, L.; Maffini-Alvaro, V.; Morand, Y.; Daranlot, J.; Rambal, N.; Previtalli, B.; Reboh, S.; Tabone, C.; Coquand, R.; Augendre, E.; Rozeau, O.; Hartmann, J. M.; Vizioz, C.; Arvet, C.; Pimenta-Barros, P.; Posseme, N.; Loup, V.; Comboroure, C.; Euvrard, C.; Balan, V.; Tinti, I.; Audoit, G.; Bernier, N.; Cooper, D.; Saghi, Z.; Allain, F.; Toffoli, A.; Faynot, O.; Vinet, M.
Source
2016 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2016 IEEE International. :17.6.1-17.6.4 Dec, 2016
Subject
Language
ISSN
2156-017X
Abstract
We report on vertically stacked horizontal Si NanoWires (NW) /»-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si/-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs /-FETs.