학술논문

An On-chip Analysis of the VLSI designs under Process Variations
Document Type
Conference
Source
2020 International Conference on Smart Electronics and Communication (ICOSEC) Smart Electronics and Communication (ICOSEC), 2020 International Conference on. :1273-1277 Sep, 2020
Subject
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Power, Energy and Industry Applications
System-on-chip
Delays
Transistors
Temperature
Temperature dependence
Threshold voltage
On-chip variations
process variation
CMOS design
AOCV
POCV
Language
Abstract
Present digital world anticipates the high performance, low cost, and low power consumption in the semiconductor industry accompanied with a rapid growth in technology. Nowadays, the economy relies on the chip system, so that the semiconductor business enters the innovation in the transistor at each hub and further this innovation comes with a lot of difficulties like reduced quality, manufacturing and multi-faceted planning. Variety with primarily random and organized combinations is one of the essential challenges in assembling the boundaries. One of the most important differences observed from these variants is on-chip variation. During this work, the on-chip variation method was briefly addressed with the aid of CMOS technology.