학술논문

Building multithreaded architectures with off-the-shelf microprocessors
Document Type
Conference
Source
Proceedings of 8th International Parallel Processing Symposium Parallel Processing Symposium, 1994. Proceedings., Eighth International. :288-294 1994
Subject
Computing and Processing
Communication, Networking and Broadcast Technologies
Buildings
Microprocessors
Yarn
Computer architecture
Hardware
Concurrent computing
Communication switching
Registers
Process design
Parallel processing
Language
Abstract
Present day parallel computers often face the problems of large software overheads for process switching and inter-processor communication. These problems are addressed by the Multi-Threaded Architecture (MTA), a multiprocessor model designed for efficient parallel execution of both numerical and non-numerical programs. We begin with a conventional processor, and add the minimal external hardware necessary for efficient support of multithreaded programs. The article begins with the top-level architecture and the program execution model. The latter includes a description of activation frames and thread synchronization. This is followed by a detailed presentation of the processor. Major features of the MTA include the Register-Use Cache for exploiting temporal locality in multiple register set microprocessors, support for programs requiring non-determinism and speculation, and local function invocations which can utilize registers for parameter passing.ETX