학술논문
Hardware synthesis for neural networks from a behavioral description with VHDL
Document Type
Conference
Author
Source
Proceedings of 1993 International Conference on Neural Networks (IJCNN-93-Nagoya, Japan) Neural networks Neural Networks, 1993. IJCNN '93-Nagoya. Proceedings of 1993 International Joint Conference on. 2:1983-1986 vol.2 1993
Subject
Language
Abstract
Presents a system for the automatic synthesis of special-purpose hardware for neural networks. Only an algorithmic description of the behaviour of the hardware and a simulation environment have to be written by the designer using VHDL. This description can be automatically mapped onto hardware using the synthesis tool CALLAS and the design system MENTOR. Using the concept of a simulation block connected to the actual design level of the hardware, implementation the consistency of the different design levels can be proved. By using reprogrammable gate arrays (FPGAs) with this system, we are able to do rapid prototyping of neural network hardware in a few days.