부산대학교 도서관

Emerging high-performance computing systems have been aggressively driving down off-chip interconnection pitch in order to satisfy their high bandwidth needs while keeping package sizes compact. This pitch scaling is expected to be below 10 microns in the near future, pushing the limits of the existing Cu-pillar with solder-cap workhorse commonly used for chip-to-substrate (C2S) applications in terms of electrical performance and thermal stability. This highlights the need for the development of an all-Cu interconnection that can be used at the C2S level and bridge the gap between the existing direct Cu-Cu bonding technologies used extensively at the wafer-to-wafer scale. GT-PRC has been developing the Cu-pillar with nanoporous-Cu (NP-Cu) cap as a technology to enable chip-to-substrate Cu-Cu interconnections. Nanoporous-Cu is a highly-reactive, solid-state, 3D-interconnected network of Cu ligaments and nodes fabricated by the selective dealloying of a Cu-Zn alloy with 40-50% Zn content co-electrodeposited using standard semi-additive processes. The low-modulus NP-Cu cap provides solder-like compliance during assembly and addresses the key challenges associated with bonding stiff Cu-Cu at the C2S scale. Assembly requires only a low-pressure placement step followed by a pressure-less batch sintering of parts to below 300°C in a reducing atmosphere to yield a void-free all-Cu bond. This paper presents the continued development of this interconnection system. A flip-chip based, flux-free “tack-bond” assembly process using the NP-Cu has been developed, and a daisy-chain test-vehicle is used to demonstrate the preliminary electrical and reliability assessment of the Cu-pillar with nanoporous-Cu caps all-Cu interconnections.