학술논문

Capacitance–Voltage Technique Based on Time Varying Magnetic Field for VDMOSFET—Part II: Measurements and Parameter Extractions
Document Type
Periodical
Source
IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 68(5):2181-2188 May, 2021
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Capacitance
Logic gates
Semiconductor device measurement
Doping
Capacitance measurement
Channel estimation
Current measurement
AC magnetic field
C<%2Fitalic>%28V<%2Fitalic>%29%22">capacitance–voltage technique C(V)
interface traps
vertical double diffusion metal–oxide–semiconductor field effect transistor (VDMOSFET) regions
Language
ISSN
0018-9383
1557-9646
Abstract
In part I, we have proposed a new capacitance–voltage technique ${C}$ ( ${V}$ ), which is simultaneously based on external ac magnetic field for surface potential modulation and on dc voltage to sweep the gate voltage. In part II, we describe the parameter extractions of vertical double diffusion metal–oxide–semiconductor field effect transistor (VDMOSFET) devices, combining the capacitance characteristics of gate–source, ${C}_{\text {GS}}$ ( ${V}_{G}$ ) and gate–drain ${C}_{\text {GD}}$ ( ${V}_{G}$ ), measured using the above cited technique, with those measured conventionally. In doing so, we have been able to extract semiconductor capacitance ( ${C}_{\text {SC}}$ ), interface trap capacitance ( ${C}_{\text {it}}$ ), doping profile concentration ${N}$ ( ${x}$ ), and interface trap density ${D}_{\text {it}}$ ( ${E}$ ) of different regions of VDMOSFET.