학술논문

Cost effective interposer for advanced electronic packages
Document Type
Conference
Source
2014 IEEE 64th Electronic Components and Technology Conference (ECTC) Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th. :1673-1678 May, 2014
Subject
Components, Circuits, Devices and Systems
Photonics and Electrooptics
Glass
Silicon
Copper
Substrates
Resistance
Arrays
Polymers
Language
ISSN
0569-5503
2377-5726
Abstract
As electronic product becomes smaller and lighter with an increasing number of function↚ the demand for high density and high integration becomes stronger.! Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wirring offer compelling benefits for 2.5D and 3D system integration;! however, they are limited by high cost and high electrical loss. On the other hand, glass has many properties that make it an ideal substrate for interposer substrates such as; ultra high resistivity, adjustable thermal expansion (CTE) and manufacturability with large panel size. Furthermore, glass via formation capabilities have dramatically improved over the past several months. Fully populated wafers with > 100,000 through holes (50pm diameter) are fabricated today with 300pm thick glass. This paper presents the demonstration of glass interposers with fine pitch through glass vias(TGV), ! with 6um RDL lithography. TGVs of 50pm in diameter and 200pm in pitch were formed successfully on 300pm thick alkali-free glass by Focused Electrical Discharging Method (FEDM). The TGVs were filled with solid Copper (Cu) using a void-free electroplating of optimized periodic pulse reverse(PPR) process and chemical mechanical polishing (CMP) as well as the TSVs. Highly insulating TGV with double side polymer insulation resulted in TGV with an insertion loss of less than 0.23dB at 20GHz. Excellent through via reliability was demonstrated, due to double side thick polymer insulator that buffers the stress created by CTE mismatch between glass, copper vias and copper traces, and TGV at 200pm pitch passed 1000 thermal cycles from −40Cdeg to 85Cdeg.