부산대학교 도서관

During the qualify stage, the yield of flip chip RF IC with multiple input and output ports was low. It is confirmed that the failure was related to RF items according to ATE test. Electrical Failure Analysis (EFA) and Physical Failure Analysis (PFA) of the failed units show that there were hot spots or breakdown damage in the NMOS within RF region . Based on a series of ESD simulation, over-voltage risk of NMOS under static-electricity was found. The following ESD test also verified the result. It is believed that the design of ESD protective circuit cannot meet the specification requirements.Removing the diode of a certain layer of ESD circuit and adding clamping circuit were needed. Meanwhile, anti-static measurements in assembly house and ATE test lab should be enhanced.