학술논문

CMOS Latch-up Improvement: Embedded Active Collector in FinFET Technology
Document Type
Conference
Source
2022 44th Annual EOS/ESD Symposium (EOS/ESD) EOS/ESD Symposium (EOS/ESD), 2022 44th Annual. EOS-44:1-6 Sep, 2022
Subject
Aerospace
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Fields, Waves and Electromagnetics
General Topics for Engineers
Photonics and Electrooptics
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
Transportation
Semiconductor device modeling
Analytical models
Sensitivity
Costs
Voltage
FinFETs
CMOS technology
Language
Abstract
An embedded active collector is proposed for CMOS latch-up improvement. The implemented structures in FinFET technology are investigated through derived analytical model, TCAD simulation, and experiments. Active collector design shows a significant latch-up improvement by enhanced holding voltage and suppressed SCR turn-on. The high holding voltage sensitivity on anode-cathode spacing and active collector area offers excellent design capability for latch-up free CMOS.