부산대학교 도서관

We present an integrated approach to on-line FPGA testing, diagnosis and fault tolerance, to be used in high-reliability and high-availability hardware. The testing and diagnostic process takes place in Self-Testing AReas (STARs) of the FPGA, without disturbing the normal system operation. The entire chip is tested by roving the STARs across the FPGA. Our approach guarantees complete testing of both logic cells and interconnect with maximum diagnostic resolution. Our multi-level fault-tolerant technique allows using partially defective logic and routing resources for normal operation, providing longer mission life in the presence of faults. In addition, our dynamic fault-tolerant method ensures that spare resources are always present in the neighborhood of the located fault, thus simplifying fault-bypassing. Our complete method has been successfully implemented and demonstrated on the ORCA 2CA series FPGAs from Lucent Technologies.