학술논문
Optimization of device dimensions for high-performance low-power architecture blocks
Document Type
Conference
Author
Source
ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705) Solid-state circuits Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European. :305-308 2003
Subject
Language
Abstract
A strategy for the implementation of energy-efficient architecture blocks is proposed. In enables mapping of algorithms to architectures at maximal efficiency based on automized optimization of device dimensions of elementary basic cells. As an example, the design of a high-throughput low-power FIR-filter is described. The effectiveness of the proposed strategy is confirmed by comparison with state-of-the-art filter macros.