부산대학교 도서관

Logic and fault simulation are crucial steps in the design process for verifying the correctness of a circuit and generating high quality manufacturing tests. Traditionally, Intel has been relying on dedicated hardware accelerators to meet its fault grading needs. The unprecedented size and complexity of the Pentium/sup (R/)Pro microprocessor were foreseen to severely stretch the existing compute resources at Intel. Exploiting the design hierarchy and using the processing power of distributed computers were identified to be key areas which could alleviate the simulation problem. This paper describes a distributed mixed level logic and fault simulator that has been developed using an RTL simulation engine at the core, in conjunction with a gate level logic/fault simulator. The techniques and algorithm developed have been successfully applied on the Pentium/sup (R/)Pro microprocessor.