학술논문
Fully-depleted-collector polysilicon-emitter SiGe-base vertical bipolar transistor on SOI
Document Type
Conference
Author
Source
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) VLSI technology VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on. :172-173 2002
Subject
Language
Abstract
A novel vertical bipolar transistor on SOI is proposed and demonstrated. The transistor operates on the principle that the collector region is fully depleted so that the charge carriers travel laterally towards the collector reachthrough and contact after traversing the intrinsic base layer. The SOI silicon layer thickness is comparable to that used in SOI CMOS, and no subcollector layer or deep trench isolation are required. Simulated device characteristics are shown. The transistor is demonstrated in a polysilicon-emitter SiGe-base npn implementation on SOI with a 140-nm silicon layer. The fabricated npn bipolar transistors exhibit a BVceo of 4.2 V and a peak f/sub T/ of over 60 GHz.