부산대학교 도서관

A 22 nm generation technology is described incorporating transistor and interconnects with performance suitable for the needs of both high density DRAM and high-performance logic devices. We have integrated a 0.029 µm 2 DRAM cell capable of meeting >100µs retention at 95°C. Results will be reported for a test-vehicle with best-reported array density at 17.5Mb/mm 2 based on a 128Mb macro. The process technology utilizes our leading edge 22nm 3-D tri-gate transistor as described previously [1,2]. The excellent leakage and performance characteristics of tri-gate transistors have been optimized for the access transistor, while maintaining the performance needed to enable high performance circuits in the same die. A high aspect-ratio, 3-D metal-insulator-metal capacitor trench has been integrated into the ultra-low-k interlayer dielectric and Cu metallization used for interconnect stacks. The previously described 22nm logic and SoC technology has been leveraged, with a 3-D MIM capacitor included in the ultra-low-k (ULK) ILD at the same level as the Metal-2 through Metal-4 interconnects. Excellent retention capability and yield have been demonstrated.