학술논문

Boolean division and factorization using binary decision diagrams
Document Type
Periodical
Source
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 13(9):1179-1184 Sep, 1994
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Data structures
Boolean functions
Logic functions
CMOS logic circuits
CMOS technology
Polynomials
Boolean algebra
Kernel
Data mining
Binary decision diagrams
Language
ISSN
0278-0070
1937-4151
Abstract
A method for performing Boolean division and factorization using a new cofactor operation, the interval cofactor, is proposed. This method Is efficiently implemented using BDD's and allows for the use of external and internal don't care sets. As well as generating a normal factored form, the method also generates an extended factored form that allows for the use of the exclusive-OR function in the expression. Using this extended form, much better factorizations may sometimes be found. The method was implemented in Catamount, a logic synthesis system currently under development. The method compares favorably to existing algebraic methods.ETX