학술논문

Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery
Document Type
Conference
Source
2022 IEEE International Reliability Physics Symposium (IRPS) Reliability Physics Symposium (IRPS), 2022 IEEE International. :1-6 Mar, 2022
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Negative bias temperature instability
Extrapolation
Thermal variables control
Life estimation
Logic gates
Market research
Interface states
NAND
DRAM
Memory Devices
Bias Temperature Instability
Interface Defects
High-Voltage
Gate Stack
Language
ISSN
1938-1891
Abstract
This paper reports BTI trends in high-voltage transistors for memory periphery devices with SiO2/Poly-Si and High-K/Metal gate stacks. For PBTI, we present an extension to the typical power law kinetics that is related to the creation of interface states due to hot electrons transported through the gate oxide. This extension enables a good fit of accelerated test data and, thereby, lifetime extrapolation. We then explore EOT and gate stack trends in PBTI. For NBTI, we report gate stack, EOT, and thermal budget trends.