부산대학교 도서관

In this work, we demonstrate a 6.9 sq. /spl mu/m embedded SRAM cell in a 0.25 /spl mu/m physical design-rule salicide high-performance CMOS technology. The scalability of this salicide-CMOS embedded-SRAM technology is demonstrated by functionality of the same SRAM cell implemented in 0.35 /spl mu/m and 0.25 /spl mu/m design rules. To our knowledge this is the smallest reported SRAM cell in a salicide-only technology, and is achieved using deep-UV lithography, shallow-trench isolation, damascene tungsten low-resistance local interconnect, and optimization of design-rules. Process and structure studies indicate process extendability to 0.18 /spl mu/m lithography generation. The CMOS technology is a 1.8 V, 0.12 /spl mu/m nominal L/sub EFF/, dual work-function CMOS with 4.0 nm gate oxide. The unloaded inverter and 2-way NAND gate delays are 24 and 45 ps respectively with 1.8 V power supply, and 57 and 98 ps with 1.0 V power supply.