학술논문

A high-performance 0.08 /spl mu/m CMOS

Document Type

Conference

Author

Su, L.; Subbanna, S.; Crabbe, E.; Agnello, P.; Nowak, E.; Schulz, R.; Rauch, S.; Ng, H.; Newman, T.; Ray, A.; Hargrove, M.; Acovic, A.; Snare, J.; Crowder, S.; Chen, B.; Sun, J.; Davari, B.

Source

1996 Symposium on VLSI Technology. Digest of Technical Papers VLSI technology VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on. :12-13 1996

Subject

Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Computing and Processing
Signal Processing and Analysis
Degradation
Delay effects

Language

Abstract

We demonstrate a 0.08 /spl mu/m CMOS suitable for high-performance (V/sub dd/=1.8 V) and low-power applications (V/sub dd/

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