학술논문
High performance CMOS devices on SOI for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering
Document Type
Conference
Author
Park, H.; Rausch, W.; Utomo, H.; Matsumoto, K.; Nii, H.; Kawanaka, S.; Fisher, P.; Oh, S.-H.; Snare, J.; Clark, W.; Mocuta, A.C.; Holt, J.; Mo, R.; Sato, T.; Mocuta, D.; Lee, B.H.; Dokumaci, O.; O'Neil, P.; Brown, D.; Suenaga, J.; Li, Y.; Brown, L.; Nakos, J.; Hathorn, K.; Ronsheim, P.; Kimura, H.; Doris, B.; Sudo, G.; Scheer, K.; Mittl, S.; Wagner, T.; Umebayashi, T.; Tsukamoto, M.; Kohyama, Y.; Cheek, J.; Yang, I.; Kuroda, H.; Toyoshima, Y.; Pellerin, J.; Schepis, D.; Agnello, P.; Welser, J.
Source
IEEE International Electron Devices Meeting 2003 Electron devices IEDM'03 Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International. :27.4.1-27.4.4 2003
Subject
Language
Abstract
We present enhanced 90 nm node CMOS devices on a partially depleted SOI with 40 nm gate length, featuring advanced process modules for manufacture, including RSD (raised source/drain), disposable spacer, final spacer for S/D doping and silicide proximity, NiSi, and thermally optimized MOL (middle-of-line) process. For the first time, we systematically designed silicide proximity in SOI and post-activation thermal cycles to improve series resistance and gate activation. This paper demonstrates decoupled effects of the individual performance boosters on drive currents and minimization of dopant deactivation, which resulted in dramatic improvement of drive currents by 11% to 19% (820 /spl mu/A/um and 420 /spl mu/A/um at Ioff = 40 nA/um with Vdd = 1.0 V, for NFET and PFET, respectively), significant reduction in effective gate oxide thickness under gate inversion by /spl sim/1.2 /spl Aring/ and /spl sim/2.1 /spl Aring/, for NFET and PFET, respectively, and an excellent inverter delay of less than 5.4 ps at Lgate of 40 nm.