학술논문
Design and performance of beam test electronics for the PHENIX Multiplicity Vertex Detector
Document Type
Conference
Author
Britton, C.L., Jr.; Bryan, W.L.; Emery, M.S.; Ericson, M.N.; Musrock, M.S.; Simpson, M.L.; Smith, M.C.; Walker, J.W.; Wintenberg, A.L.; Young, G.R.; Allen, M.D.; Clonts, L.G.; Jones, R.L.; Kennedy, E.J.; Smith, R.S.; Baissevain, J.; Jacak, B.V.; Jaffe, D.; Kapustinsky, J.S.; Simon-Gillo, J.; Sullivan, J.P.; Van Hecke, P.; Xu, N.
Source
1996 IEEE Nuclear Science Symposium. Conference Record Nuclear science and medical imaging Nuclear Science Symposium, 1996. Conference Record., 1996 IEEE. 1:6-10 vol.1 1996
Subject
Language
ISSN
1082-3654
Abstract
The system architecture and test results of the custom circuits and beam test system for the Multiplicity-Vertex Detector (MVD) for the PHENIX detector collaboration at the Relativistic Heavy Ion Collider (RHIC) are presented in this paper. The final detector per-channel signal processing chain will consist of a preamplifier-gain stage, a current-mode summed multiplicity discriminator, a 64-deep analog memory (simultaneous read-write), a post-memory analog correlator, and a 10-bit 5 /spl mu/s ADC. The Heap Manager provides all timing control, data buffering, and data formatting for a single 256-channel multi-chip module (MCM). Each chip set is partitioned into 32-channel sets. Beam test (16-cell deep memory) performance for the various blocks will be presented as well as the ionizing radiation damage performance of the 1.2 /spl mu/ n-well CMOS process used for preamplifier fabrication.