학술논문
Extended 0.13 /spl mu/m CMOS technology for the ultra high-speed and MS/RF application segments
Document Type
Conference
Author
Chang, C.S.; Chao, C.P.; Leung, Y.K.; Lin, C.H.; Hsu, H.-M.; Wang, Y.P.; Chang, S.Y.; Chiu, T.H.; Shyu, J.S.; Wu, C.C.; Wang, C.H.; Chang, R.Y.; Chen, C.W.; Huang, C.F.; Chen, C.H.; Chen, S.H.; Yeh, T.H.; Cheng, J.Y.; Liaw, J.J.; Chu, Y.L.; Ong, T.C.; Yu, M.C.; Yu, C.H.; Lin, H.J.; Tao, H.J.; Liang, M.S.; See, Y.C.; Diaz, C.H.; Sun, Y.C.
Source
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) VLSI technology VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on. :68-69 2002
Subject
Language
Abstract
This paper introduces new technology features to support ultra high-speed and MS/RF applications incorporated into a leading-edge fully manufacturable 0.13 /spl mu/m CMOS foundry technology (K.K. Young et al, IEDM Tech Digest, pp. 563-566, 2000). New core devices with 15.5 /spl Aring/ and nominal 75 nm physical gate lengths support at least 10% performance improvement with respect to prior release. These devices offer the best I/sub off/-I/sub dsat/ performance reported so far for 1.2 V applications. To support high-speed I/O standards, additional 1.8 V-32 /spl Aring/ I/O devices are integrated with the 15.5 /spl Aring/ transistors. Leading-edge passive elements for MS/RF applications are reported in this work. Advanced Cu/low-k back end process integration that can support up to nine layers of metal is also demonstrated.