학술논문

A W-Band 2 × 2 Phased-Array Transmitter With Digital Gain-Compensation Technique
Document Type
Periodical
Source
IEEE Transactions on Circuits and Systems I: Regular Papers IEEE Trans. Circuits Syst. I Circuits and Systems I: Regular Papers, IEEE Transactions on. 71(4):1558-1571 Apr, 2024
Subject
Components, Circuits, Devices and Systems
Phase shifters
Transmitters
Radio frequency
Power amplifiers
Phased arrays
Insertion loss
Topology
Phased-array transmitter
vector-sum phase shifter
variable-gain power amplifier (VGPA)
low gain/phase error
W-band
Language
ISSN
1549-8328
1558-0806
Abstract
In this paper, a W-band $2\times 2$ phased-array transmitter with digital gain compensation is proposed to minimize amplitude and angle errors of synthesized beams. The RF phase-shifting architecture is utilized for the phased-array transmitter to reduce circuit blocks and lower system complexity. The high-resolution phase shifting is achieved by a vector-sum phase shifter, which is based on a quadrature-all-pass filter (QAF) with compensation network and Gilbert-type variable gain amplifiers (VGAs) with digital-controlled current digital-to-analog converters (I-DACs). To lower the gain error introduced by the phase shifter in RF phase-shifting architecture, the variable-gain power amplifier (VGPA) is proposed. The gain of the VGPA is finely adjusted to compensate the gain variation of phase shifter in different phase states. Meanwhile, the phase variation of the VGPA under variable gain states is optimized to avoid the influence on phase errors. To verify the aforementioned mechanism, a W-band $2\times 2$ phased-array transmitter is implemented and fabricated in a conventional 40-nm CMOS technology. Based on the digital gain-compensation technique, the phased-array transmitter exhibits a less than 1.12dB RMS gain error and less than 1.82° RMS phase error. In addition, the fabricated chip achieves 8.13dBm peak saturated output power and better than 9dB power gain with 135mW power consumption for each channel.