학술논문

Thermally-Aware Layout Design of β-Ga₂O₃ Lateral MOSFETs
Document Type
Periodical
Source
IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 69(3):1251-1257 Mar, 2022
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Logic gates
Metals
Thermal conductivity
Temperature measurement
Conductivity
Substrates
Performance evaluation
Electro-thermal modeling
gallium oxide
MOSFET
nanoparticle-assisted Raman thermometry
self-heating
thermal characterization
Language
ISSN
0018-9383
1557-9646
Abstract
$\beta $ -phase gallium oxide ( $\beta $ -Ga 2 O 3 ) is drawing significant attention in the power electronics field due to its remarkable critical electric field strength [greater than gallium nitride (GaN) and silicon carbide (SiC)] and the availability of high-quality melt-grown substrates providing the opportunity for low-cost manufacturing. However, because of the low thermal conductivity of $\beta $ -Ga 2 O 3 , thermal management strategies at the device-level are required to achieve the targeted high-power capabilities. In this work, the effects of the anisotropic thermal conductivity of $\beta $ -Ga 2 O 3 and the geometrical design of the metal electrodes/interconnects on the device self-heating were investigated. For a power density ( ${P}_{\text {dis}}$ ) of 1 W/mm at ${V}_{\text {GS}} =$ 4 V (i.e., a fully open channel condition), when the channel width is along a direction perpendicular to ( $\bar {{2}}{01}$ ), the channel temperature decreases by 10% as compared to a case aligning the channel length along the direction close to [100]. Also, by decreasing the width of the interconnect between the drain electrode and the metal bond pad (serving as a heat pathway) from 100 to $10~\mu \text{m}$ (90% reduction), the channel temperature increased by ~8% for ${P}_{\text {dis}} =$ 1 W/mm. Last, for devices with identical heat generation profiles, increasing the distance between the gate and drain contact from 1 to 10 $\mu \text{m}$ , results in a 35% increase in the channel temperature rise. This work highlights the importance of thermally aware device layout design for lateral $\beta $ -Ga 2 O 3 transistors, in terms of maximizing both the electrical and thermal performance.