학술논문

A Case for In-Memory Random Scatter-Gather for Fast Graph Processing
Document Type
Periodical
Source
IEEE Computer Architecture Letters IEEE Comput. Arch. Lett. Computer Architecture Letters. 23(1):73-77 Jan, 2024
Subject
Computing and Processing
Random access memory
Computer architecture
Standards
Memory management
Bandwidth
Random sequences
Protocols
Accelerator architectures
in-memory computing
memory architecture
parallel processing
random access memory
Language
ISSN
1556-6056
1556-6064
2473-2575
Abstract
Because of the widely recognized memory wall issue, modern DRAMs are increasingly being assigned innovative functionalities beyond the basic read and write operations. Often referred to as “function-in-memory”, these techniques are crafted to leverage the abundant internal bandwidth available within the DRAM. However, these techniques face several challenges, including requiring large areas for arithmetic units and the necessity of splitting a single word into multiple pieces. These challenges severely limit the practical application of these function-in-memory techniques. In this paper, we present Piccolo, an efficient design of random scatter-gather memory. Our method achieves significant improvements with minimal overhead. By demonstrating our technique on a graph processing accelerator, we show that Piccolo and the proposed accelerator achieves $1.2-3.1 \times$1.2-3.1× speedup compared to the prior art.