부산대학교 도서관

MBIST is a standard mechanism to test memory arrays and potentially detect all of the faults that may be present inside the memory cells using an effective collection of algorithms. However, a massive number of memory cells wrapped by BIST logic can result in substantial overhead in wiring, gate area and also be detrimental to memory performance. Therefore, new MBIST designs for advanced SoCs that address the challenges must be explored to reduce the overall cost of manufacturing tests. It is important to choose the appropriate BIST architecture and algorithmic coverage for a range of array sizes to get the products to market in the quickest fashion. March 5n algorithm in previous is proven to achieve shorter test time than conventional MATS++ algorithms without penalizing the fault coverage. Moreover, the algorithm is capable of covering inversion coupling faults. The fault coverage of the previous March 5n algorithm is extended and proved in this work. An improved March 5n architecture is proposed to extend its properties in terms of repair capabilities while incurring minimal area overhead expenses. The proposed work improved the March 5n MBIST architecture by nearly 8% of maximum operating frequency and repair capabilities with the trade-off of area overhead increment by about 4%.