학술논문

Aging-aware dynamic voltage or frequency scaling
Document Type
Conference
Source
Design of Circuits and Integrated Systems Design of Circuits and Integrated Circuits (DCIS), 2014 Conference on. :1-6 Nov, 2014
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Sensors
Delays
Degradation
Clocks
Logic gates
Aging
Latches
Dynamic voltage frequency scaling
Performance sensors
Power and performance optimization
PVTA variations
Language
Abstract
The work developed consists in an aging-aware dynamic voltage or frequency scaling methodology, to be used in long-term operation, using global and local performance sensors. Methodology allows circuits to be dynamically optimized, during their life-time, according to one of two possible needs: (1) restrict power consumption, by reducing power-supply voltage to the minimum value that prevents errors from happening; or (2) optimize performance, by increasing operating frequency to the maximum limit that prevents errors' occurrence. The dynamic optimization is achieved by using a cooperative work of global and local sensors. Moreover, a new local sensor is presented, to obtain an enhanced solution with additional tolerance to delay-faults, allowing to achieve higher improvement in power or frequency optimization, or to achieve a higher safety and control margin. Spice simulations in a 65nm CMOS technology demonstrate the results for an example of a dynamic frequency scaling strategy.