학술논문
Formal verification using parametric representations of Boolean constraints
Document Type
Conference
Author
Source
Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361) Design automation 99 Design Automation Conference, 1999. Proceedings. 36th. :402-407 1999
Subject
Language
Abstract
We describe the use of parametric representations of Boolean predicates to encode data-space constraints and significantly extend the capacity of formal verification. The constraints are used to decompose verifications by sets of case splits and to restrict verifications by validity conditions. Our technique is applicable to any symbolic simulator. We illustrate our technique on state-of-the-art Intel(R) designs, without removing latches or modifying the circuits in any way.