학술논문
Stress reduction in high voltage MIS capacitor fabrication
Document Type
Conference
Source
2017 International Symposium on Power Electronics (Ee) Power Electronics (Ee), 2017 International Symposium on. :1-6 Oct, 2017
Subject
Language
Abstract
Metal-insulator-semiconductor capacitors used as a RC snubber attenuate voltage overshoots which may occur during switching phases. These devices feature good temperature stability up to 200°C and can be integrated very close to power switches on the same transfer substrate. As the capacitors need to withstand high voltages in most applications, thick dielectric layers have to be used, causing significant amount of wafer bow during processing. A dielectric stress compensation structure on the back side of the wafers is therefore introduced and shown to reduce the resulting wafer bow by up to 50%. Planar MIS capacitors using a 1 μm thick dielectric layer stack achieve dielectric breakdown voltages of up to 1000 V along with capacitance densities of 5.4 nF/cm 2 . In comparison, devices with a dielectric layer thickness of 250 nm exhibit a capacitance density of 13.6 nF/cm 2 and a resulting dielectric breakdown voltage of 250 V.