학술논문
Design of high performance PFETs with strained si channel and laser anneal
Document Type
Conference
Author
Source
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. International Electron Devices Meeting 2005 Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International. :489-492 2005
Subject
Language
ISSN
0163-1918
2156-017X
2156-017X
Abstract
The effects of the integration of two major PFET performance enhancers, embedded SiGe (e-SiGe) junctions and compressively stressed nitride liner (CSL) have been examined systematically. The additive effects of e-SiGe and CSL have been demonstrated, enabling high performance PFET (drive current of 640 muA/mum at 50 nA/mum off state current at 1V) with only modest Ge incorporation (~20 at. %) in S/D. And for the first time, we have demonstrated that by integrating e-SiGe and laser anneal (LA), defect-free e-SiGe can be fabricated, and the benefits of both techniques can be retained. Our study of geometric effects also reveals that e-SiGe can be extended to 45 nm technology and beyond