부산대학교 도서관

This paper introduces a framework for system level debugging and monitoring for advanced embedded System-on-Chip architectures that may include evolvable and reconfigurable elements and have very tight power constraints. While current debug solutions are highly dependant on off-line configuration and interrogation through a developer, the new framework introduces an AI-lead infrastructure that can potentially reduce much of the development effort. The framework complements the debug circuits in the current generation while enhancing them with a higher level functionality that examines and monitors system activity on-line.