학술논문

ADRA: Extending Digital Computing-In-Memory With Asymmetric Dual-Row-Activation
Document Type
Periodical
Source
IEEE Transactions on Circuits and Systems II: Express Briefs IEEE Trans. Circuits Syst. II Circuits and Systems II: Express Briefs, IEEE Transactions on. 70(8):3089-3093 Aug, 2023
Subject
Components, Circuits, Devices and Systems
FeFETs
Nonvolatile memory
Memory management
Arithmetic
Boolean functions
Standards
Sensors
Computing-in-memory
FeFET
in-memory subtraction
in-memory comparison
Language
ISSN
1549-7747
1558-3791
Abstract
In this letter, we propose an asymmetric dual row activation scheme called ADRA for enhancing digital computing-in-memory (CiM) based on in-memory operands. ADRA solves the many-to-one mapping problem of input vectors to output voltages faced by previous CiM techniques, enabling (a) simultaneous single-cycle memory read and CiM of primitive Boolean functions (b) computation of any Boolean function and (c) CiM of non-commutative functions such as subtraction and comparison. While the proposed technique is technology-agnostic, we show its utility for ferroelectric transistor (FeFET)-based non-volatile memory. Compared to the standard near-memory computation, we show that our method can achieve a full scale two-operand digital CiM using just one memory access, leading to a 23.2% - 72.6% decrease in energy-delay product (EDP).