학술논문
Area and power efficient carry-select adder
Document Type
Conference
Source
2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) Recent Trends in Electronics, Information & Communication Technology (RTEICT), IEEE International Conference on. :1897-1901 May, 2016
Subject
Language
Abstract
In this paper an area and power efficient design for 1 bit and 8 bit Carry Select Adder (CSLA) has been proposed. Conventional and other CSLAs are designed using a traditional full adder, which has complexity in terms of area and power consumption. So to overcome this problem a new technique is implemented on the CSLA. Moreover the logic gates are designed based on the Gate Diffusion Input (GDI) technique. In this paper the Power and Area of modified CSLA is compared with the conventional CSLA and the D-Latch based CSLA. The proposed design reduces the complexity in area as well as the power consumption. The power for 1-bit is reduced by 42.7% and 99% when compared with conventional CSLA and D-Latch based CSLA respectively and the power for 8-bit is reduced by 93.9% and 93.4% when compared with conventional CSLA and D-Latch based CSLA respectively. It has been designed using Cadence Virtuoso tools with 90-nm CMOS process Technology. The simulation results shows that the GDI design performs better when compared with the CMOS logic design.