학술논문
EDA approaches in identifying latchup risks
Document Type
Conference
Author
Source
2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2016 38th. :1-11 Sep, 2016
Subject
Language
Abstract
In this paper we review latchup protection verification methods and EDA challenges. We demonstrate complex static and transient latchup scenarios requiring advanced connectivity analysis. Using various EDA verification flows and tools we study latchup problems associated with grounded n-wells, biased n-wells and parasitic thyristors formed during ESD events.