학술논문
2.5 /spl Omega///spl square/ W/TiN/poly stack gate technology for high density and embedded DRAM technology
Document Type
Conference
Author
Source
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) VLSI technology, systems, and applications VLSI Technology, Systems, and Applications, 1999. International Symposium on. :247-250 1999
Subject
Language
ISSN
1524-766X
Abstract
A W/TiN/Poly gate stack has been developed and extensively characterized, and it is applied to a 0.2 /spl mu/m CMOS transistor design for Gigabit and embedded DRAM technology. The gate sheet is less than 2.5 /spl Omega///spl square/ with a 600 /spl Aring//200 /spl Aring//900 /spl Aring/ W/TiN/Poly gate stack at 0.16 /spl mu/m line width. The effective oxide thickness is found to be 3 /spl Aring/ thicker than a comparable poly-only gate. The oxide hard breakdown field can exceed 12 MV/cm and CHC lifetime is greater than 10 years with the W/TiN/Poly gate stack technology. In addition, a drive current of 400 /spl mu/A//spl mu/m for nMOS and 190 /spl mu/A//spl mu/m for pMOS have been achieved at 1 pA//spl mu/m off-current and 1.8 V Vcc with 5 nm gate oxide. This is the highest drive current reported to date for similar technologies.