학술논문
Very high voltage planar devices using field plate and semi-resistive layers: design and fabrication
Document Type
Conference
Author
Source
2000 International Semiconductor Conference. 23rd Edition. CAS 2000 Proceedings (Cat. No.00TH8486) Semiconductor conference Semiconductor Conference, 2000. CAS 2000 Proceedings. International. 1:363-366 vol.1 2000
Subject
Language
Abstract
An efficient junction termination technique for 4 kV devices is presented. The complementarity of a field plate and a semi-resistive layer is shown allowing us to fabricate planar devices with a very high breakdown voltage and to decrease the silicon area consumed. The dynamic behaviour of SIPOS terminated diodes is physically explained and modelled. A solution to improve the dynamic behaviour up to 3000 V//spl mu/s is proposed. The following describes the complete design, electrical characteristics and fabrication of 4 kV planar diodes.