부산대학교 도서관

A 130nm CMOS evaluation chip intended to read Silicon strip detectors has been designed and successfully tested. Optimized for a detector capacitance of 10 pF, it includes four channels of a full signal processing chain, including low-noise charge integration and pulse shaping, a 16 deep-analog sampler triggered on an analogue sum of adjacent inputs, and a parallel 10-bit analog to digital conversion. Laboratory and in-situ tests results of the chip are reported, demonstrating the behavior and performance of the full sampling process and analog to digital conversion, on a laboratory test stand, and from radioactive source as well as beam tests. Each channel occupies an area of 100 × 600 square microns on Silicon, and dissipates less than half a milliwatt of static power.