학술논문

Novel High-Resolution Fully FPGA-based Detection Setup for High-Transfer Rate Time-Resolved Experiments
Document Type
Conference
Source
2022 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC) Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2022 IEEE. :1-4 Nov, 2022
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Nuclear Engineering
Photonics and Electrooptics
Signal Processing and Analysis
Application specific integrated circuits
Instruments
X-ray lasers
Detectors
Computer architecture
Logic gates
Field programmable gate arrays
Time-to-Digital Converter (TDC)
Cross Delay-Lines (CDL)
Field Programmable Gate Array (FPGA)
Time-Resolved Experiments.
Gigabit Transceiver
Language
ISSN
2577-0829
Abstract
With the advancement of new X-ray sources, such as synchrotron radiation facilities and Free Electron Lasers (FELs), which can generate high-flux and ultrashort X-ray pulses, time-resolved techniques have become general and powerful tools for exploring structural dynamics of matter. Thus, a new generation of acquisition system is needed, where the ability to temporally solve each measurement with great precision and versatility is required. Among the instruments most involved in this direction there are undoubtedly the particle detectors, which can no longer limit themselves to providing images but must be able to associate temporal information to each event received, in addition to the spatial one. With this in mind, Cross Delay-Lines (CDLs) detectors are among the most suitable and promising solutions allowing both spatial and temporal data to be acquired simultaneously. Typical architectures underlying the acquisition electronics of these detectors rely on an Application Specific Integrated Circuit (ASIC) Time-to-Digital Converter (TDC) followed by a Field Programmable Gate Array (FPGA) for data processing. The lack of reconfigurability and the inadequacy of adapting to different applications given by the ASIC, has brought us to study a new solution. Our multi-year work proposes a fully FPGA-based architecture with the purpose of obtaining excellent time resolution and fast parallel computing while maintaining the full flexibility only an FPGA can achieve. The acquisition chain is comprised of two FPGA boards, one hosting a custom-made TDC while the other the necessary image reconstruction algorithm. Over the years we managed to design an 8-channel TDC with a precision of 12 ps r.m.s, 5 ns dead-time, and 4 ps of non-linearity reaching a spatial resolution of 30/40 μm FWHM on the CDL. Improvements to the connection between the TDC and the image processing board are been implemented allowing a transfer rate of tens Gb/s, which means hundreds of Mmeasures/s.