부산대학교 도서관

In this paper, we are going to present a Digital-to-Time Delay-line (DTC-DL) IP-Core, capable of detecting the rising edge of an asynchronous and aperiodic input signal, and replicating it at its output, with a dynamically programmable delay. This solution is compatible with Xilinx 28-nm 7-Series Field Programmable Gate Array (FPGA) and System-on-Chip (SOC) devices. Compared to Application Specific Integrated Circuit (ASIC) solutions, the one proposed in this work features high flexibility, low hardware overhead, and, in particular, re-programmability; which makes the IP-Core adaptable to many applications and, above all, upgradable without a complete redesign of the system. The DTC-DL is based on the concept of Nutt-Interpolation, combining a synchronous Coarse Logic and an asynchronous Fine Logic. This interpolation allows to have both a resolution in the order of tens of picoseconds, and maximum delay of hundreds of milliseconds. The output jitter is kept below a few tens of picoseconds r.m.s. thanks to an architecture using only one IDELAY primitive instance per channel, calibrated thanks to the IDELAYCTRL primitive, which is given by Xilinx. The DTC-DL IP-Core has been successfully validated on a custom board entirely developed at Politecnico di Milano, hosting a Xilinx Artix-7 XC7A100TFTG256-2.