부산대학교 도서관

This paper presents a new version of the FAST family of ASICs and its comparison with the previous version. The new design, FAST3, aims at a timing jitter below 15 picoseconds when coupled to Ultra-Fast Silicon detectors (UFSD). The FAST3 integrated circuit is designed in standard 110 nm CMOS technology; it comes in two different versions: the amplifier-comparator version comprises 20 readout channels, while the amplifier-only version 16 channels. The ASIC power rail is at +1.2 V, and the power consumption for the front-end stage is 2.4 mW/ch and about 5 mW/ch for the output driver. In our tests, the FAST2 ASIC, coupled to a UFDS with a capacitance of 3.4 pF, achieves timing jitters of about 25 ps at an input charge of about 15 fC, while the simulation indicates that the FAST3 jitter will be about 15 ps at the same charge. Furthermore, FAST3 enhances its dynamic range up to 55 fC compared to the 15 fC of FAST2.