부산대학교 도서관

This paper presents the FAST2 family of ASICs. FAST2 aims to keep the jitter below 20 picoseconds when coupled to Ultra-Fast Silicon detectors (UFSD). FAST2 is designed in standard 110 nm CMOS technology, and it comes in 2 versions: the amplifier-comparator version comprises 20 readout channels while the amplifier-only version of 16 channels. The ASIC power rail is at +1.2 V, and its power consumption is 2.4 mW/ch. In our tests, the FAST2 ASIC, coupled to a UFDS with a capacitance of 3.4 pF, achieves timing jitters lower than 15 ps, at an input charge of about 15 fC. In tests with an Sr90 beta source, the FAST2 reached a time resolution below 45 ps.The worst case of Near-end and Far-end crosstalk due to the mutual capacitance between neighboring channels achieves an amplitude of -23 dB at 50 W of load.