부산대학교 도서관

Modern RF communication technologies often shift the baseband processing to the digital domain, thus requiring an analog-to-digital converter (ADC) as interfacing element. For most applications, those ADCs must provide very-high conversion rate at low cost (effective in terms of area and power). We propose an improved binary-search ADC topology, which relies on a pipeline of threshold-reconfigurable comparators and a time-interleaved track-and-hold arrangement. We also propose a topology of threshold-reconfigurable comparator and a corresponding effective design methodology based on optimization through genetic algorithms. In this paper, we design a proof-of-concept 5-bit ADC which does not require calibration as most similar designs. Monte Carlo simulations for the proposed design show that, sampling at 1.5 GSps, the ADC consumes 5 mW providing 4.6 effective bits and a figure of merit of 138 fJ/conversion step (mean values).