부산대학교 도서관

With the development of industries, such as high-performance computing, advanced driver-assistance systems, artificial intelligence, and deep learning, demand for high-bandwidth memory, and chiplets continues to increase. Most of these applications generally use a source-synchronous single-ended parallel transceiver architecture and consist of a 2.5D package (called an advanced package) along with silicon interposer channels [1]. Applications also include a lot of high-speed I/O to process large amounts of data. In general, to achieve high-speed operation and high performance, bandwidth extension techniques, such as inductors and a continuous-time linear equalizer, and calibration schemes, such as slicer-offset calibration and skew calibration, between data and clock have been used in high-speed transceivers. However, these schemes are difficult to implement for applications that require many high-speed transceivers in a small area. For example, if an RX uses a quarter-rate architecture for high-speed operation, each slicer in the RX requires offset-calibration circuits, which require a significant area and static power consumption. Therefore, equalization techniques and the training schemes that can be implemented with low power and small area are being developed. Further, a 2D package, called standard package, with package substrate channels is being reviewed as an alternative to the advanced package for cost competitiveness [2–5]. In this work, we implement a 4nm 48Gb/s/wire single-ended NRZ parallel transceiver for next-generation memory interfaces and chiplets using standard package. The TX adopts an IQ clock divider with a high-speed clock and reset generator (HCRG) that prevents abnormal operations. We implement an on-chip Tx feedback equalizer, with a reduced feedback time and propose a duty-cycle corrector with cross-coupled inverters to minimize settling time and eliminate dynamic voltage stress. For the RX, digitally-controlled offset-calibration circuits are implemented, for each slicer, to reduce static-power consumption and area. Training algorithms for offset calibration are controlled by software. The transceiver in a 4nm FinFET CMOS technology operates up to 4 Gb/s/wire with a 10mm package substrate channel and achieves a 1.66Tb/s/mm beach-front bandwidth.