학술논문

On methods for ordering sparse matrices in circuit simulation
Document Type
Conference
Author
Source
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196) Circuits and systems Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on. 5:315-318 vol. 5 2001
Subject
Components, Circuits, Devices and Systems
Communication, Networking and Broadcast Technologies
Engineered Materials, Dielectrics and Plasmas
Sparse matrices
Circuit simulation
Equations
Symmetric matrices
Computational efficiency
Computational modeling
Circuit testing
Genetic mutations
Computational complexity
Software performance
Language
Abstract
Recently proposed methods for ordering sparse symmetric matrices are discussed and their performance is compared with that of the Minimum Degree and the Minimum Local Fill algorithms. It is shown that these methods applied to symmetrized modified nodal analysis matrices yield orderings significantly better than those obtained from the Minimum Degree and Minimum Local Fill algorithms, in some cases at virtually no extra computational cost.