학술논문
X-Masking for Deterministic In-System Tests
Document Type
Periodical
Author
Source
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 42(11):4260-4269 Nov, 2023
Subject
Language
ISSN
0278-0070
1937-4151
1937-4151
Abstract
Deterministic in-system tests begin to play an essential role in safety-critical applications, in large data centers, or in monitoring silicon aging, to name just a few. All of these ecosystems require periodic, high-quality tests to assure required test coverage and short test application, especially in designs that must test themselves during system operations. In order for deterministic tests to be in-system applicable, they should compact multimillion-bit test responses with unknown ( $\rm X$ ) values to small signatures. This, in turn, allows for a much faster input-only streaming and a simultaneous reduction of the on-chip-stored test data volume, a system memory, and test time. Typically, the unknown states, whose sources vary from uninitialized memories to unpredictable last-minute timing violations, render signatures unusable. Hence, test response compaction requires some form of protection. This article presents a user-tunable X-masking scheme. It works synergistically with on-chip test compression logic by employing encoded test data to completely filter out unknown values that otherwise might reach a test response compactor, such as a multiple-input signature register or test result sticky bits used by the on-chip compare framework. It makes the proposed scheme a very versatile of its kind. Experimental results obtained for several industrial cores show feasibility and efficiency of the proposed scheme altogether with the actual impact of X-masking on various test-related statistics.