학술논문
A 1.0625 $\sim$ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS
Document Type
Periodical
Author
Source
IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 46(12):3126-3139 Dec, 2011
Subject
Language
ISSN
0018-9200
1558-173X
1558-173X
Abstract
A 14.025 Gb/s multi-media transceiver employs on-die Rx AC coupling with baseline wander correction and equalizes up to 26 dB insertion loss at 14.025 Gb/s with a linear equalizer, 10-tap DFE, and 4-tap Tx FIR filter in SST driver. The proposed techniques enable direct feedback for 1st-tap ISI cancellation, and positions of four DFE taps to be adapted over the range of 7 to 38 UI. The prototype is realized in 40 nm CMOS, consumes 410 mW at worst case, and has passed 16GFC compliance tests at 14.025 Gb/s.