부산대학교 도서관

The rapid increase in processor and memory integration onto a single die continues to place increasingly complex demands on the interconnect network. In addition to providing low latency, high speed and high bandwidth access from all processors to all shared resources, the burdens of hardware cache coherence and resource virtualization are being placed upon the interconnect as well. This paper describes a multi-core shared memory controller interconnect (MSMC) which supports up to 12processors, 8 independent banks of IO-coherent on-chip shared RAM, an IO-coherent external memory controller, and high bandwidth IO connections to the SoC infrastructure. MSMC also provides basic IO address translation and memory protection for the on-chip shared SRAM and external memory as well as soft error protection with hardware scrubbing for the on-chip memory. MSMC formed the heart of the compute cluster for a28-nm CMOS device including 8 Texas Instruments C66x DSP processors and 4 cache-coherent ARM A15 processors sharing 6MB of on-chip SRAM running at 1.3 Ghz. At this speed MSMCprovides all connected masters a combined read/write bandwidth of nearly 1TB/s to access a combined read/write bandwidth of457.6 GB/s to all shared resources @ 16 mm2.