학술논문

Enabling Low-Power Charge-Domain Nonvolatile Computing-in-Memory (CIM) With Ferroelectric Memcapacitor
Document Type
Periodical
Source
IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 71(4):2404-2410 Apr, 2024
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Capacitance
Logic gates
PIN photodiodes
Junctions
Electrodes
Dielectrics
Power demand
Binary neural network (BNN)
computing-in-memory (CIM)
ferroelectricity
memcapacitor
multiplication and accumulation (MAC)
Language
ISSN
0018-9383
1557-9646
Abstract
The explosive growth in data-centric computing driven by artificial intelligence (AI) and big data has surpassed the capabilities of the traditional von Neumann architecture. The architectural separation of computing and memory units results in substantial energy consumption, latency, and additional hardware expenses. Therefore, a novel computing paradigm with low power consumption and high parallelism is urgently needed. One promising solution to address the memory wall challenge is capacitor-based computing-in-memory (CIM). In this article, we propose a hafnium-based ferroelectric memcapacitor (FE-memcap), which achieves a 103 ON/ OFF ratio by combining ferroelectric polarization switching and p-i-n junction charge shielding. Furthermore, gate work-function engineering enables high ON/ OFF ratios with small driven voltages, typically around 0.05 V. When integrated into the XNOR-binary neural network (BNN), the FE-memcap demonstrates the equivalent computational accuracy as traditional memristor-based counterparts. Importantly, the FE-memcap exhibits negligible static power consumption and significantly reduces dynamic power consumption by over 104 times. This attribute renders it highly suitable for event-driven edge computing applications and augments its potential for future AI applications.